FY21-1 KEK/Lapis 0.20um SOI CMOS Pixel MPW run (MX2263)

Last updat Mar 16, 2023


Floore Plan

What's New

Deadline of expression of interest : July 31, 2021
Fix submission, mask area and cost: Aug. 31, 2021
Deadline of submission : Nov. 21, 2021
finish wafer process : end of Mar. 2022.
finish backside process and dicing : end of May 2022.
Scheduled delivery of chips : beginning of June.



   Send following files to Yasuo Arai (yasuo.arai@kek.jp) via e-mail or through internet server;

=== Notes on this MPW run ===


Other Documents


User Cell Libraries

(Please use these at your own risk.)


Please use following Pad-Pin Wiring assignment as much as possible if you want standard packaging.

Design Tips (by Y.Arai)



Price List

* MPW run Base Price (22 bare chips)

2,800 kYen/2.9x2.9 mm2 chip

5.300 kYen/4.45x4.45 mm2 chip

8,800 kYen/6.0x6.0 mm2 chip

Other size: negotiable

Academic user can receive 30%~50% discount from above prices. The discount rate will depend on total requested chip area and budget joining this MPW run. You may be able to get more chips in case less than 50% discount where we duplicate chip design in a mask to fulfill the mask area.

* Additional chips (22 bare chips) from different wafer in the MPW run

250 kYen/2.9x2.9 mm2 chip

500 kYen/6.0x6.0 mm2 chip

Other size: negotiable

* Cost for Packaging

under negotiation

* Additional Wafer run for a single user (temprally)

'1,300 kYen(process+wafer)' /wafer for HR1(CZn) wafer

'1,320 kYen(process) + 71.5 kYen(wafer)' /wafer for FZn wafer

'1,420 kYen(process) + 150 kYen(wafer)' /wafer for Doubel-SOI wafer

For Japanese user : Consumption Tax will be added to above price.

For Overseas user : Handled by H-REPIC Co. Ltd. Shipping and handling fee will be added to above price.

Mailing List

Useful References

If you find any problem in this page, please contact to takeda@astro.miyazaki-u.ac.jp or yasuo.arai@kek.jp